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ultralow distortion if vga ad8375 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features bandwidth of 630 mhz (?3 db) gain range: ?4 db to +20 db step size: 1 db 0.2 db differential input and output noise figure: 8 db @ maximum gain output ip3 of ~50 dbm at 200 mhz output p1db of 19 dbm at 200 mhz provides constant sfdr vs. gain parallel 5-bit control interface power-down feature single 5 v supply operation 24-lead, 4 mm 4 mm lfcsp applications differential adc drivers high if sampling receivers wideband multichannel receivers instrumentation functional block diagram a2 a3a4 a1 a0 post-amp registers and gain decoder v pos comm ad8375 v com vin+ vin? pwup out+ out+ out? out? 06724-001 figure 1. general description the ad8375 is a digitally controlled, variable gain, wide bandwidth amplifier that provides precise gain control, high ip3, and low noise figure. the excellent distortion performance and high signal bandwidth make the ad8375 an excellent gain control device for a variety of receiver applications. using an advanced high speed sige process and incorporating proprietary distortion cancellation techniques, the ad8375 achieves 50 dbm output ip3 at 200 mhz. the ad8375 provides a broad 24 db gain range with 1 db resolution. the gain is adjusted through a 5-pin control interface and can be driven using standard ttl levels. the open-collector outputs provide a flexible interface, allowing the overall signal gain to be set by the loading impedance. thus, the signal voltage gain is directly proportional to the load. the ad8375 is powered on by applying the appropriate logic level to the pwup pin. the quiescent current of the ad8375 is typically 130 ma. when powered down, the ad8375 consumes less than 5 ma and offers excellent input-to-output isolation. fabricated on an analog devices, inc., high speed sige process, the ad8375 is supplied in a compact, thermally enhanced, 4 mm 4 mm, 24-lead lfcsp package and operates over the temperature range of ?40c to +85c. ? 40 ?60 ?50 ?70 ?90 ?80 ?100 ?110 65 55 60 50 40 45 35 30 harmonic distortion (dbc), output @ 2v p-p oip3 (dbm), output @ 3dbm/tone 40 60 80 100 120 140 160 180 200 frequency (mhz) 06724-052 oip3 hd2 hd3 figure 2. harmonic distortion and output ip3 vs. frequency
ad8375 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 circuit description ......................................................................... 12 basic structure ............................................................................ 12 applications ..................................................................................... 13 basic connections ...................................................................... 13 single-ended-to-differential conversion ............................... 13 broadband operation ................................................................ 14 adc interfacing ......................................................................... 14 layout considerations ............................................................... 17 characterization test circuits .................................................. 17 evaluation board ........................................................................ 18 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 8/07revision 0: initial version
ad8375 rev. 0 | page 3 of 24 specifications v s = 5 v, t = 25c, r s = r l = 150 at 140 mhz, 2 v p-p differential output, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out < 2 v p-p (5.2 dbm) 630 mhz slew rate 5 v/ns input stage pin vin+ and pin vin? maximum input swing for linear operation (a v = ?4 db) 8.5 v p-p differential input resistance differential 125 150 165 common-mode input voltage 1.9 v cmrr gain code = 00000 55 db gain amplifier transconductance gain code = 00000 0.060 0.067 0.074 s maximum voltage gain gain code = 00000 20 db minimum voltage gain gain code 11000 ?4 db gain step size from gain code = 00000 to 11000 0.89 0.98 1.01 db gain flatness all gain codes, 20% fractional bandwidth for f c < 200 mhz 0.12 db gain temperature sensitivity gain code = 00000 8 mdb/c gain step response for v in = 100 mv p-p, gain code = 10100 to 00000 5 ns output stage pin vout+ and pin vout? output voltage swing at p1db, gain code = 00000 12.6 v p-p output impedance differential 16||0.8 k||pf noise/harmonic performance 46 mhz gain code = 00000 noise figure 8.3 db second harmonic v out = 2 v p-p ?92 dbc third harmonic v out = 2 v p-p ?94 dbc output ip3 2 mhz spacing, +3 dbm per tone 50 dbm output 1 db compression point 22 dbm 70 mhz gain code = 00000 noise figure 8.3 db second harmonic v out = 2 v p-p ?98 dbc third harmonic v out = 2 v p-p ?95 dbc output ip3 2 mhz spacing, 3 dbm per tone 51 dbm output 1 db compression point 22 dbm 140 mhz gain code = 00000 noise figure 8.3 db second harmonic v out = 2 v p-p ?90 dbc third harmonic v out = 2 v p-p ?100 dbc output ip3 2 mhz spacing, 3 dbm per tone 51 dbm output 1 db compression point 20 dbm 200 mhz gain code = 00000 noise figure 8.3 db second harmonic v out = 2 v p-p ?85 dbc third harmonic v out = 2 v p-p ?92 dbc output ip3 2 mhz spacing, 3 dbm per tone 50 dbm output 1 db compression point 19 dbm
ad8375 rev. 0 | page 4 of 24 parameter conditions min typ max unit power interface supply voltage 4.5 5.0 5.5 v vpos and output quiescent current thermal connectio n made to exposed paddle under device 120 125 130 ma vs. temperature ?40c t a +85c 150 ma power-down current pwup low 2.5 ma vs. temperature ?40c t a +85c 3 ma power-up/gain control pin a0 to pin a4, pin pwup v ih minimum voltage for a logic high 1.6 v v il maximum voltage for a logic low 0.8 v logic input bias current 900 na table 2. gain code vs. voltage gain look-up table 5-bit binary gain code voltage gain (db) 00000 +20 00001 +19 00010 +18 00011 +17 00100 +16 00101 +15 00110 +14 00111 +13 01000 +12 01001 +11 01010 +10 01011 +9 01100 +8 5-bit binary gain code voltage gain (db) 01101 +7 01110 +6 01111 +5 10000 +4 10001 +3 10010 +2 10011 +1 10100 0 10101 ?1 10110 ?2 10111 ?3 11000 ?4 >11000 ?4
ad8375 rev. 0 | page 5 of 24 absolute maximum ratings table 3. parameter rating supply voltage, v pos 5.5 v pwup, a0 to a4 ?0.6 v to (v pos + 0.6 v) input voltage, v in+ , v in? ?0.15 v to +4.15 v dc common mode vcom 0.25 v vcom 6 ma internal power dissipation 825 mw ja (exposed paddle soldered down) 63.6c/w jc (at exposed paddle) 14.6c/w maximum junction temperature 130c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad8375 rev. 0 | page 6 of 24 pin configuration and fu nction descriptions pin 1 indicator 1 vcom 2 vin+ 3 vin? 4 a4 5 a3 6 a2 15 vout+ 16 vout? 17 vout+ 18 vout? 14 comm 13 vpos 7 a 1 8 a 0 9 v p o s 1 1 c o m m 1 2 v p o s 1 0 v p o s 2 1 c o m m 2 2 c o m m 2 3 v p o s 2 4 c o m m 2 0 c o m m 1 9 p w u p 06724-002 ad8375 top view (not to scale) figure 3. 24-lead lfcsp table 4. pin function descriptions pin no. mnemonic description 1 vcom common-mode pin. typically bypassed to ground using external capacitor. 2 vin+ voltage input positive. 3 vin? voltage input negative. 4 a4 msb for the 5-bit gain control interface. 5 a3 msb ? 1 for the gain control interface. 6 a2 msb ? 2 for the gain control interface. 7 a1 lsb + 1 for the gain control interface. 8 a0 lsb for the 5-bit gain control interface. 9, 10, 12, 13, 23 vpos positive supply pins. should be bypassed to ground using suitable bypass capacitor. 11, 14, 20, 21, 22, 24 comm device common (dc ground). 15, 17 vout+ positive output pins (open collec tor). require dc bias of +5 v nominal. 16, 18 vout? negative output pins (open coll ector). require dc bias of +5 v nominal. 19 pwup chip enable pin. enabled with a logic high and disabled with a logic low.
ad8375 rev. 0 | page 7 of 24 typical performance characteristics v s = 5 v, t a = 25c, r s = r l = 150 , 2 v p-p output, maximum gain unless otherwise noted. 25 20 10 15 5 0 ?10 ?5 gain (db) ?4 11000 0 10100 5 01111 10 01010 15 00101 20 00000 gain code 06724-003 46mhz 70mhz 140mhz 200mhz figure 4. gain vs. gain code at 46 mhz, 70 mhz, 140 mhz, and 200 mhz 25 20 15 10 5 0 ?5 ?10 gain (db) 10 100 1000 frequency (mhz) 06724-004 20db 19db 18db 17db 16db 15db 14db 13db 12db 11db 10db 9db 8db 7db 6db 5db 4db 3db 2db 1db 0db ?1db ?2db ?3db ?4db figure 5. gain vs. frequency response 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 gain error (db) ?4 11000 0 10100 5 01111 10 01010 15 00101 20 00000 gain code 06724-005 25c 85c ?40c figure 6. gain error over temperature at 140 mhz 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 gain error (db) ?4 11000 0 10100 5 01111 10 01010 15 00101 20 10100 gain code 06724-006 figure 7. gain step error, frequency 140 mhz 25 20 15 10 5 0 op1db (dbm) ?4 1 6 11 16 21 gain (db) 06724-007 200mhz 140mhz 70mhz 46mhz input max rating boundary figure 8. p1db vs. gain at 46 mhz, 70 mhz, 140 mhz, and 200 mhz 25 20 15 10 5 0 op1db (dbm) 46 100 150 200 250 300 350 400 450 500 frequency (mhz) 06724-008 +25c +85c ?40c figure 9. p1db vs. frequency at maximum gain, three temperatures
ad8375 rev. 0 | page 8 of 24 52 51 50 49 48 47 46 45 44 43 42 41 40 30 50 70 90 110 130 150 170 190 210 frequency (mhz) oip3 (dbm) a v = 0db a v = ?4db a v = +10db a v = +20db 06724-009 figure 10. output third-order intercept at four gains, output level at 3 dbm/tone 52 51 50 49 48 47 46 45 44 43 42 41 40 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 p out (dbm) oip3 (dbm) 06274-010 a v = 0db a v = ?4db a v = +10db a v = +20db figure 11. output third-order intercept vs. power at four gains, frequency 140 mhz +25c +85c ?40c 70 60 65 55 45 50 40 30 35 oip3 (dbm) 40 60 80 100 120 140 160 180 200 frequency (mhz) 06724-011 figure 12. output third-order intercept vs. frequency, three temperatures, output level at 3 dbm/tone 25 30 35 40 45 50 55 ?3?2?1012345 35 40 45 50 55 60 65 oip3 (dbm) 06724-012 p out per tone (dbm) oip3 (dbm) a v = 20db a v = 0db +25c 20db ?40c 20db +85c 20db +25c 0db ?40c 0db +85c 0db figure 13. output third-order intercept vs. power, frequency 140 mhz, three temperatures ? 70 ?80 ?75 ?85 ?95 ?90 ?100 ?110 ?105 imd3 (dbc) ?4 1 6 11 16 gain (db) 06724-013 46mhz 70mhz 140mhz 200mhz figure 14. two-tone output imd vs. gain at 46 mhz, 70 mhz, 140 mhz, and 200 mhz, output level at 3 dbm/tone +25c +85c ?40c ? 70 ?80 ?75 ?85 ?95 ?90 ?100 ?110 ?105 imd3 (dbc) 40 60 80 100 120 140 160 180 200 frequency (mhz) 06724-014 figure 15. two-tone output imd vs. frequency, three temperatures, output level at 3 dbm/tone
ad8375 rev. 0 | page 9 of 24 ? 75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ? 65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 harmonic distortion hd2 (dbc) harmonic distortion hd3 (dbc) 40 60 80 100 120 140 160 180 200 frequency (mhz) 06724-015 hd2 ?4db hd2 0db hd2 +10db hd2 +20db hd3 ?4db hd3 0db hd3 +10db hd3 +20db figure 16. harmonic distortion vs. frequency at four gain codes, v out = 2 v p-p ?80 ? 75 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ? 60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 harmonic distortion hd2 (dbc) harmonic distortion hd3 (dbc) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 p out (dbm) 06724-016 hd2 +20db hd2 +10db hd2 0db hd2 ?4db hd3 +20db hd3 +10db hd3 0db hd3 ?4db figure 17. harmonic distortion vs. power at four gain codes, frequency 140 mhz ? 80 ?85 ?90 ?95 ?100 ?105 harmonic distortion hd2 and hd3 (dbc) 40 60 80 100 120 140 160 180 200 frequency (mhz) hd2 +25c hd3 +25c hd2 ?40c hd3 ?40c hd2 +85c hd3 +85c 06274-017 figure 18. harmonic distortion vs. frequency, three temperatures, v out = 2 v p-p ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ? 85 ?5?4?3?2?1012345 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ? 70 harmonic distortion hd3 (dbc) 06724-018 p out (dbm) harmonic distortion hd2 (dbc) hd3 +25c hd3 +85c hd3 ?40c hd2 ?40c hd2 +25c hd2 +85c figure 19. harmonic distortion vs. power, frequency 140 mhz, three temperatures 35 30 25 20 15 10 5 0 noise figure (db) ?4?2 0 2 4 6 8 101214161820 gain (db) 06724-019 46mhz 70mhz 140mhz 200mhz figure 20. nf vs. gain at 46 mhz, 70 mhz, 140 mhz, and 200 mhz 45 40 35 30 25 20 15 10 5 0 0 100 200 300 400 500 600 700 800 900 1000 frequency (mhz) noise figure (db) 06724-020 a v = 0db a v = ?4db a v = +10db a v = +20db figure 21. nf vs. frequency
ad8375 rev. 0 | page 10 of 24 06724-021 ch1 500mv ? ch2 500mv ? m10.0ns 10.0gs/s it 10.0ps/pt a ch1 960mv 1 2 figure 22. gain step time domain response 06724-022 ch1 500mv ? ch2 500mv ? m20.0ns 10.0gs/s it 20.0ps/pt a ch1 960mv 1 2 figure 23. enbl time domain response r4 06724-023 m2.5ns 20.0gs/s it 10.0ps/pt a ch4 28.0mv r3 r1 ref1 position ?420mv/div ref1 scale 2v 0pf 10pf each side input ref1 2.0v 2.5ns figure 24. pulse response to capacitive loading, gain ?4 db 06724-024 m2.5ns 20.0gs/s it 10.0ps/pt a ch4 28.0mv r3 ref3 position ?600mv/div ref3 scale 500mv 0pf input r1 10pf each side ref3 500mv 2.5ns figure 25. pulse response to capacitive loading, gain 20 db 06724-025 input output ref1 50.0mv ref1 ch2 500mv m2.5ns 20gsps it 2.5ps/pt a ch2 ?610mv 2 ref1 position ?1.02/div ref1 scale 50mv rise (c2) 1.384ns fall(c2) 1.39ns figure 26. large signal pulse response 0 ?5 ?10 ?15 ?20 ?25 ?30 180 120 60 0 ?60 ?120 ?180 10 100 1000 frequency (mhz) s11 mag (db) s11 phase (degrees) 06724-026 figure 27. s11 vs. frequency
ad8375 rev. 0 | page 11 of 24 0 ?20 ?40 ?60 ?80 ?100 ?120 0 100 200 300 400 500 600 700 800 900 1000 frequency (mhz) s12 (db) 06724-027 figure 28. reverse isolation vs. frequency 0 ?20 ?40 ?60 ?80 ?100 ?120 0 100 200 300 400 500 600 700 800 900 1000 frequency (mhz) isolation (db) 06724-028 figure 29. off-state isolation vs. frequency 1.00e?09 9.00e?10 8.00e?10 7.00e?10 6.00e?10 5.00e?10 4.00e?10 3.00e?10 2.00e?10 1.00e?10 0.00e+00 delay (seconds) 0 100 200 300 400 500 600 700 800 900 1000 frequency (mhz) 06724-029 +20db +10db 0db ?4db figure 30. group delay vs. frequency at gain 80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 frequency (mhz) cmrr (db) 06724-031 figure 31. common-mode reje ction ratio vs. frequency
ad8375 rev. 0 | page 12 of 24 circuit description basic structure the ad8375 is a differential variable gain amplifier consisting of a 150 digitally controlled passive attenuator followed by a highly linear transconductance amplifier. 06724-032 gm core amp mux buffers ad8375 a0 to a4 digital select attenuator vin+ vcom vin? vout+ vout? figure 32. simpli fied schematic input system the dc voltage level at the inputs of the ad8375 is set by an internal voltage reference circuit to about 2 v. this reference is accessible at vcom and can be used to source or sink 100 a. for cases where a common-mode signal is applied to the inputs, such as in a single-ended application, an external capacitor between vcom and ground is required. the capacitor improves the linearity performance of the part in this mode. this capacitor should be sized to provide a reactance of 10 or less at the lowest frequency of operation. if the applied common-mode signal is dc, its amplitude should be limited to 0.25 v from vcom (vcom 0.25 v). the device can be powered down by pulling the pwup pin down to below 0.8 v. in the powered down mode, the total current reduces to 3 ma (typical). the dc level at the inputs and at vcom remains at about 2 v, regardless of the state of the pwup pin. output amplifier the gain is based on a 150 differential load and varies as r l is changed per the following equations: voltage gain = 20 (log( r l /150) + 1) and power gain = 10 (log( r l /150) + 2) the dependency of the gain on the load is due to the open- collector architecture of the output stage. the dc current to the outputs of the amplifier is supplied through two external chokes. the inductance of the chokes and the resistance of the load determine the low frequency pole of the amplifier. the parasitic capacitance of the chokes adds to the output capacitance of the part. this total capacitance in parallel with the load resistance sets the high frequency pole of the device. generally, the larger the inductance of the choke, the higher its parasitic capacitance. therefore, the value and type of the choke should be chosen keeping this trade-off in mind. for operation frequency of 15 mhz to 700 mhz driving a 150 load, 1 h chokes with srf of 160 mhz or higher are recommended (such as 0805ls-102xjbb from coilcraft). the supply current consists of about 50 ma through the vcc pin and 80 ma through the two chokes combined. the latter increases with temperature at about 2.5 ma per 10c. there are two output pins for each polarity and they are oriented in an alternating fashion. when designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. a good practice is to avoid any ground or power plane under this routing region and under the chokes to minimize the parasitic capacitance. gain control a 5-bit binary code changes the attenuator setting in 1 db steps such that the gain of the device changes from 20 db (code 0) to ?4 db (code 24 and higher). the noise figure of the device is about 8 db at maximum gain setting and it increases as the gain is reduced. the increase in noise figure is equal to the reduction in gain. the linearity of the part measured at the output is first-order independent of the gain setting. from 0 db to 20 db gain, oip3 is approximately 50 dbm into 150 load at 140 mhz (3 dbm per tone). at gain settings below 0 db, it drops to approximately 45 dbm.
ad8375 rev. 0 | page 13 of 24 applications basic connections figure 35 shows the basic connections for operating the ad8375. a voltage between 4.5 v and 5.5 v should be applied to the supply pins. each supply pin should be decoupled with at least one low inductance, surface-mount ceramic capacitor of 0.1 f placed as close as possible to the device. the outputs of the ad8375 are open collectors that need to be pulled up to the positive supply with 1 h rf chokes. the differential outputs are biased to the positive supply and require ac coupling capacitors, preferably 0.1 f. similarly, the input pins are at bias voltages of about 2 v above ground and should be ac-coupled as well. the ac coupling capacitors and the rf chokes are the principle limitations for operation at low frequencies. to enable the ad8375, the pwup pin must be pulled high. taking pwup low puts the ad8375 in sleep mode, reducing current consumption to 5 ma at ambient. single-ended-to-differential conversion the ad8375 can be configured as a single-ended input to differential output driver as shown in figure 33 . a 150 resistor in parallel with the input impedance of input pin provides an impedance matching of 50 . the voltage gain and the bandwidth of this configuration, using a 150 load, remains the same as when using a differential input. 5 0.1f 0.1f 0.1f 0.1f 37.5 ? 150? ad8375 1h 150? a0 to a4 1h +5 v 06724-035 vcm 0.1f 50? ac figure 33. single-ended-t o-differential conversion using a single-ended input decreases the power gain by 3 db and limits distortion cancellation. consequently, the second- order distortion is degraded. the third-order distortion remains low to 200 mhz, as shown in figure 34 . 06724-036 ? 60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 harmonic distortion (dbc) 0 200 150 100 50 frequency (mhz) hd2 hd3 figure 34. harmonic distortion vs. frequency of single-ended-to-differential conversion parallel control interface 0.1f 0.1f 0.1f r s 2 r s 2 ac balanced source 0.1f 0.1f +v s r l balanced load 1h 1h 0.1f 0.1f 0.1f 10f + v s 06724-034 comm vpos comm comm comm pwup 19 24 23 22 21 20 a1 a0 vpos vpos comm vpos 12 7891011 18 17 16 15 14 13 1 2 3 4 5 6 vcom vin+ vin? a4 a3 a2 vout? vout+ vout? vout+ comm vpos ad8375 figure 35. basic connections
ad8375 rev. 0 | page 14 of 24 broadband operation the ad8375 uses an open-collector output structure that requires dc bias through an external bias network. typically, choke inductors are used to provide bias to the open-collector outputs. choke inductors work well at signal frequencies where the impedance of the choke is substantially larger than the target ac load impedance. in broadband applications, it may not be possible to find large enough choke inductors that offer enough reactance at the lowest frequency of interest while offering a high enough self resonant frequency (srf) to support the maximum bandwidth available from the device. the circuit in figure 36 can be used when frequency response below 10 mhz is desired. this circuit replaces the bias chokes with bias resistors. the bias resistor has the disadvantage of a greater ir drop, and requires a supply rail that is several volts above the local 5 v supply used to power the device. additionally, it is necessary to account for the ac loading effect of the bias resistors when designing the output interface. whereas the gain of the ad8375 is load dependent, r l , in parallel with r1 + r2, should equal the optimum 150 target load impedance to provide the expected ac performance depicted in the data sheet. additionally, to ensure good output balance and even-order distortion performance, it is essential that r1 = r2. 5 0.1f 0.1f 0.1f 0.1f 50 ? etc1-1-13 37.5 ? 37.5 ? 5v ad8375 set to 5v r1 r2 vr vr rl a0 to a4 06724-037 figure 36. single-ended broadband operation with resistive pull-ups using the formula for r1 (equation 1), the values of r1 = r2 that provide a total presented load impedance of 150 can be found. the required voltage applied to the bias resistors, vr, can be found by using the vr formula (equation 2). 150 75 ? = l l r r r1 (1) and 5 10 40 3 + = ? r1 vr (2) for example, in the extreme case where the load is assumed to be high impedance, r l = , the equation for r1 reduces to r1 = 75 . using the equation for vr, the applied voltage should be vr = 8 v. the measured single-tone low frequency harmonic distortion for a 2 v p-p output using 75 resistive pull-ups is provided in figure 37. ? 80 ?82 ?84 ?86 ?88 ?90 ?92 ?94 ?96 harmonic distortion (dbc) 0 5 10 15 20 frequency (mhz) hd2 hd3 06724-038 figure 37. harmonic distortion vs. frequency using resistive pull-ups adc interfacing the ad8375 is a high output linearity variable gain amplifier that is optimized for adc interfacing. the output ip3 and noise floor essentially remain constant vs. the 24 db available gain range. this is a valuable feature in a variable gain receiver where it is desirable to maintain a constant instantaneous dynamic range as the receiver gain is modified. the output noise density is typically around 20 nv/hz, which is comparable to 14-/16- bit sensitivity limits. the two-tone ip3 performance of the ad8375 is typically around 50 dbm. this results in sfdr levels of better than 86 db when driving the ad9445 up to 140 mhz. there are several options available to the designer when using the ad8375. the open-collector output provides the capability of driving a variety of loads. figure 38 shows a simplified wideband interface with the ad8375 driving a ad9445. the ad9445 is a 14-bit 125 msps analog-to-digital converter with a buffered wideband input, which presents a 2 k differential load impedance and requires a 2 v p-p differential input swing to reach full scale. 0.1f 0.1f 5 0 ? etc1-1-13 37.5 ? 37.5 ? 0.1f 0.1f 0.1f 0.1f 82 ? 82 ? 1h 5v 1h 5 v 33 ? 33 ? 14 ad9445 14-bit adc ad8375 5 a0 to a4 06724-039 l (series) l (series) vin+ vin? figure 38. wideband adc interfacing example featuring the ad9445
ad8375 rev. 0 | page 15 of 24 for optimum performance, the ad8375 should be driven differentially using an input balun or impedance transformer. figure 38 uses a wideband 1:1 transmission line balun followed by two 37.5 resistors in parallel with the 150 input imped- ance of the ad8375 to provide a 50 differential terminated input impedance. this provides a wideband match to a 50 source. the open-collector outputs of the ad8375 are biased through the two 1 h inductors and are ac-coupled to the two 82 load resistors. the 82 load resistors in parallel with the series-terminated adc impedance yields the target 150 differential load impedance, which is recommended to provide the specified gain accuracy of the device. the load resistors are ac-coupled from the ad9445 to avoid common-mode dc loading. the 33 series resistors help to improve the isolation between the ad8375 and any switching currents present at the analog-to-digital sample and hold input circuitry. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 (dbfs) 0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 frequency (mhz) 06724-040 snr = 64.93dbc sfdr = 86.37dbc noise floor = ?108.1db fund = ?1.053dbfs second = ?86.18dbc third = ?86.22dbc 1 2 3 4 5 6 + figure 39. measured single-tone performance of the circuit in figure 38 for a 100 mhz input signal the circuit depicted in figure 38 provides variable gain, isolation and source matching for the ad9445. using this circuit with the ad8375 in a gain of 20 db (maximum gain) an sfdr performance of 86 dbc is achieved at 100 mhz, as indicated in figure 39 . the addition of the series inductors l (series) in figure 38 extends the bandwidth of the system and provides response flatness. using 100 nh inductors as l (series), the wideband system response of figure 40 is obtained. the wideband frequency response is an advantage in broadband applications such as predistortion receiver designs and instrumentation applications. however, by designing for a wide analog input frequency range, the cascaded snr performance is somewhat degraded due to high frequency noise aliasing into the wanted nyquist zone. 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 (dbfs) 20 48 76 104 132 160 188 216 244 272 300 frequency (mhz) first point = ?2.93dbfs end point = ?9.66dbfs mid point = ?2.33dbfs min = ?9.66dbfs max = ?1.91dbfs 06724-041 figure 40. measured frequenc y response of wideband adc interface depicted in figure 38 an alternative narrow-band approach is presented in figure 41 . by designing a narrow band-pass antialiasing filter between the ad8375 and the target adc, the output noise of the ad8375 outside of the intended nyquist zone can be attenuated, helping to preserve the available snr of the adc. in general, the snr improves several db when including a reasonable order antialias- ing filter. in this example, a low loss 1:3 input transformer is used to match the ad8375s 150 balanced input to a 50 unbal- anced source, resulting in minimum insertion loss at the input.
ad8375 rev. 0 | page 16 of 24 figure 41 is optimized for driving some of analog devices popular unbuffered adcs, such as the ad9246 , ad9640 , and ad6655 . table 5 includes antialiasing filter component recommendations for popular if sampling center frequencies. inductor l5 works in parallel with the on-chip adc input capacitance and a portion of the capacitance presented by c4 to form a resonant tank circuit. the resonant tank helps to ensure the adc input looks like a real resistance at the target center frequency. additionally, the l5 inductor shorts the adc inputs at dc, which introduces a zero into the transfer function. in addition, the ac coupling capacitors and the bias chokes introduce additional zeros into the transfer function. the final overall frequency response takes on a band-pass characteristic, helping to reject noise outside of the intended nyquist zone. table 5 provides initial suggestions for prototyping purposes. some empirical optimization may be needed to help compensate for actual pcb parasitics. 5 1nf 1nf 1nf 1nf 50 ? 1:3 ad8375 301 ? c2 a0 to a4 06724-042 c4 1h 1h l1 l1 l3 l3 cml 165 ? 165 ? l5 ad9246 ad9640 ad6655 figure 41. narrow-band if sampling solution for unbuffered adc application table 5. interface filter recommendation s for various if sampling frequencies center frequency 1 db bandwidth l1 c2 l3 c4 l5 96 mhz 27 mhz 390 nh 5.6 pf 390 nh 25 pf 100 nh 140 mhz 30 mhz 330 nh 3.3 pf 330 nh 20 pf 56 nh 170 mhz 32 mhz 270 nh 2.7 pf 270 nh 20 pf 39 nh 211 mhz 32 mhz 220 nh 2.2 pf 220 nh 18 pf 27 nh
ad8375 rev. 0 | page 17 of 24 layout considerations there are two output pins for each polarity, and they are oriented in an alternating fashion. when designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. a good practice is to avoid any ground or power plane under this routing region and under the chokes to minimize the parasitic capacitance. characterization test circuits differential-to-differential characterization the s-parameter characterization for the ad8375 was performed using a dedicated differential input to differential output characterization board. figure 44 shows the layout of characterization board. the board was designed for optimum impedance matching into a 75 system. because both the input and output impedances of the ad8375 are 150 differentially, 75 impedance runs were used to match 75 network analyzer port impedances. on-board 1 h inductors were used for output biasing, and the output board traces were designed for minimum capacitance. 0.1f 0.1f 06724-046 l1 1h l2 1h 0.1f 0.1f +5v 5 a0 to a4 ac 75 ? traces 75 ? traces 75 ? 75 ? 75 ? 75 ? ac ad8375 figure 42. test circuit for s-parameters on dedicated 75 differential-to-differential board 0.1f 0.1f tc3-1t 06724-047 t1 0.1f 0.1f 330? 330? 25 ? 25 ? 50? +9 v 5 a0 to a4 50? 96? 96? ac ad8375 figure 43. test circuit for time domain measurements 06724-044 figure 44. differential-to-differential characterization board circuit side layout c1 0.1f c2 0.1f tc3-1t ad8375 06724-043 t1 l1 1h l2 1h c3 0.1f c4 0.1f r1 62 ? r2 62 ? r4 25 ? r3 25 ? etc1-1-13 t2 50? pad loss = 11db +5 v 5 a0 to a4 50? ac figure 45. test circuit for distortion, gain, and noise
ad8375 rev. 0 | page 18 of 24 evaluation board figure 46 shows the schematic of the ad8375 evaluation board. the silkscreen and layout of the component and circuit sides are shown in figure 47 through figure 50 . the board is powered by a single supply in the 4.5 v to 5.5 v range. the power supply is decoupled by 10 f and 0.1 f capacitors at each power supply pin. additional decoupling, in the form of a series resistor or inductor at the supply pins, can also be added. table 6 details the various configuration options of the evaluation board. the output pins of the ad8375 require supply biasing with 1 h rf chokes. both the input and output pins must be ac- coupled. these pins are converted to single-ended with a pair of baluns (mini-circuits tc3-1t+ and m/a-com etc1-1-13). the balun at the input, t1, is used to transform a 50 source impedance to the desired 150 reference level. the output balun, t3, and the matching components are configured to provide a 150 to 50 impedance transformation with an insertion loss of about 11 db.
ad8375 rev. 0 | page 19 of 24 wa0 wa1 wa2 wa3 wa4 c20 10f vpos c14 0.1f c13 0.1f vpos c1 0.1f c11 0.1f c2 0.1f tc3-1t+ t1 r70 r71 r72 r25 30.9 ? r24 r23 30.9 ? r2 0 ? r1 r9 0 ? r10 0 ? inp inn t3 c8 0.1f c7 0.1f r20 61.9 ? r91 0 ? r19 61.9 ? l2 1h l1 1h c63 0.1f c64 0.1f r15 0 ? r16 0 ? vpos vpos r62 c62 0.1f etc1-1-13 r29 r30 0 ? outn outp c5 vpos pu r13 0 ? vpos 06724-045 vxa comm vpos comm comm comm pwup 19 24 23 22 21 20 a1 a0 vpos vpos comm vpos 12 7891011 18 17 16 15 14 13 1 2 3 4 5 6 vcom vin+ vin? a4 a3 a2 vout? vout+ vout? vout+ comm vpos ad8375 c60 0.1f figure 46. ad8375 evaluation board schematic
ad8375 rev. 0 | page 20 of 24 table 6. evaluation board configuration options components function default conditions c13, c14, c20, c63, c64, r91 power supply decoupling. nominal supply decoupling consists a 10 f capacitor to ground followed by 0.1 f capacitors to ground positioned as close to the device as possible. c20 = 10 f (size 3528) c13, c14, c63, c64 = 0.1 f (size 0402) r91 = 0 (size 0402) t1, c1, c2, c60, r1, r2, r9, r10, r70 to r72 input interface. t1 is a 3:1 impedance ratio balun to transform a 50 single- ended input into a 150 balanced differen tial signal. r2 grounds one side of the differential drive interface for single-ended applications. r9, r10, and r70 to r72 are provided for generic placement of matching components. c1 and c2 are dc blocks. t1 = tc3-1+ (mini-circuits) c1, c2, c60 = 0.1 f (size 0402) r2, r9, r10 = 0 (size 0402) r1, r70 to r72 = open (size 0402) t3, c7, c8, c62 l1, l2, r15, r16, r19, r20, r23 to r25, r29, r30, r62 output interface. c7 and c8 are dc blocks . l1 and l2 provide dc biases for the output. r19, r20, and r23 to r25 are provided for generic placement of matching components. the evaluation boa rd is configured to provide a 150 to 50 impedance transformation with an insertion loss of about 11 db. t3 is a 1:1 impedance ratio balun to transform the balanced differential signal to a single-ended signal. r30 grounds one side of the differential output interface for single-ended applications. t3 = etc1-1-13 (m/a-com) c7, c8, c62 = 0.1 f (size 0402) l1, l2 = 1 h (size 0805) r19, r20 = 61.9 (size 0402) r23, r25 = 30.9 (size 0402) r15, r16 = 0 (size 0603) r30 = 0 (size 0402) r24, r29, r62 = open (size 0402) pu, r13, c5 enable interface. the ad8375 is enabled by applying a logic high voltage to the pwup pin. the device is disabled when the pu switch is set in the position closest to the pu label, connecting the pwup pin to ground. the device is enabled when the pu switch is set in the opposite position, connecting the pwup to vpos. pu = installed r13 = 0 (size 0603) c5 = open (size 0603) wa0 to wa4 parallel interface control. used to hardwire a0 through a4 to the desired gain. the bank of switches, wa4 to wa0, set the binary gain code. wa4 represents the lsb. wa0 represents the msb. wa0 to wa4 = installed c11 voltage reference. input common-mode voltage ac-coupled to ground by 0.1 f capacitor, c11. c11 = 0.1 f (size 0402)
ad8375 rev. 0 | page 21 of 24 06724-048 figure 47. component side silkscreen 06724-049 figure 48. circuit side silkscreen 06724-050 figure 49. component side layout 06724-051 figure 50. circuit side layout
ad8375 rev. 0 | page 22 of 24 outline dimensions 1 24 6 7 13 19 18 12 2.25 2.10 sq 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vggd-2 figure 51. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad8375acpz-wp 1 ?40c to +85c 24-lead lead frame chip scale package [lfcsp_vq], waffle pack cp-24-1 ad8375acpz-r7 1 ?40c to +85c 24-lead lead frame chip scale package [lfcsp_vq], 7 reel cp-24-1 AD8375-EVALZ 1 evaluation board 1 z = rohs compliant part.
ad8375 rev. 0 | page 23 of 24 notes
ad8375 rev. 0 | page 24 of 24 t notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06724-0-8/07(0) ttt

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